1. Technical Field
The present invention relates to semiconductor nanowire field effect transistors (FETs) and, in particular, to vertically stacked nanowire devices having double gate planar FETs and methods for making the same.
2. Description of the Related Art
Silicon nanowire-based metal oxide semiconductor field effect transistors (MOSFETs) are of interest due to their superior electrostatics. Semiconductor nanowire field effect transistors have been fabricated by generating a collection of nanowires and then placing them where desired (known as a bottom-up approach) or through lithographic patterning. However, for nanowires with small diameters, achieving the high layout density required for a competitive technology is challenging. For example, a nanowire field effect transistor (FET) with a body diameter of 10 nm would require a layout pitch of less than 32 nm simply to match the channel width density of planar devices. Reducing the body diameter to 5 nm reduces the required pitch to roughly 15 nm. This is well beyond the range of what optical lithography can currently provide, even with pitch doubling techniques.
Additionally, despite the advantages of nanowires, their small diameter is significantly limiting with respect to current carrying capacity. Furthermore, it can be difficult to form existing nanowire technologies on the same chip with other structures.